Labros Bisdounis

Δημοσιεύσεις σε πρακτικά διεθνών συνεδρίων

Σ1. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, C. Goutis, Modeling the CMOS short-circuit power dissipation, IEEE International Symposium on Circuits and Systems (ISCAS), Atlanta, USA, May 1996, pp. IV.469-IV.472.

Σ2. L. Bisdounis, O. Koufopavlou, S. Nikolaidis, Accurate evaluation of the CMOS short-circuit power dissipation for short-channel devices, IEEE International Symposium on Low-Power Electronics and Design (ISLPED), Monterey, USA, August 1996, pp. 189-192.

Σ3. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, CMOS short-circuit power dissipation including velocity saturation and gate-to-drain capacitive coupling, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Bologna, Italy, September 1996, pp. 157-166.

Σ4. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, C. Goutis, Accurate timing model for the CMOS inverter, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Rodos, Greece, October 1996, pp. 89-92.

Σ5. A. Rjoub, L. Bisdounis, O. Koufopavlou, Influence of the nMOS and pMOS transistor threshold voltages on CMOS circuits power dissipation, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Cairo, Egypt, December 1997, pp. 545-549.

Σ6. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, Delay evaluation of static CMOS gates for short-channel devices, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Cairo, Egypt, December 1997, pp. 532-536.

Σ7. L. Bisdounis, S. Nikolaidis, O. Koufopavlou, C. E. Goutis, Switching response modeling of the CMOS inverter for submicron devices, IEEE Design, Automation and Test in Europe Conference (DATE), Paris, France, February 1998, pp. 729-735.

Σ8. L. Bisdounis, O. Koufopavlou, Modeling the dynamic behavior of series-connected MOSFETs for delay analysis of multiple-input CMOS gates, IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, USA, June 1998, pp. VI.342-VI.345.

Σ9. L. Bisdounis, O. Koufopavlou, Analytical modeling of short-circuit energy dissipation in submicron CMOS structures, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Paphos, Cyprus, September 1999, pp. 1667-1670.

Σ10. L. Bisdounis, Energy-aware system-on-chip (SoC) design for 5 GHz WLANs, 2nd Workshop of Central Marketplace for Dissemination of Low-power Microelectronics Design Knowledge (MARLOW), Turin, Italy, September 2003, paper no. 6 (invited lecture).

Σ11. F. Menichelli, M. Olivieri, L. Benini, M. Donno, L. Bisdounis, A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design, IEEE Design, Automation and Test in Europe Conference (DATE), Paris, France, February 2004, vol. 3, pp. 312-317.

Σ12. L. Bisdounis, Short-circuit energy dissipation model for sub-100nm CMOS buffers, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Athens, Greece, December 2010, pp. 615-618.

Σ13. L. Bisdounis, An accurate and compact MOSFET I-V model for nanometer CMOS circuit analysis, Panhellenic Conference on Electronics and Telecommunications (PACET), Thessaloniki, Greece, March 2012, paper no. S3.5.

Σ14. L. Bisdounis, Efficient baseband modem physical implementation for fixed broadband wireless access networks, IEEE International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, Greece, May 2016, paper no. 17.

Δημοσιεύσεις σε πρακτικά διεθνών συνεδρίων που εκδόθηκαν ως βιβλία

Σ15. S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, L. Bisdounis, Instrumentation set-up for instruction-level power modeling, pp. 71-80, in Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science Series, No. 2451, edited by B. Hochet, A. J. Acosta and M. J. Bellido, Springer, September 2002 (International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS, Seville, Spain, September 2002).

Σ16. S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis, S. Blionas, Instruction-level energy modeling for pipelined processors, pp. 279-288, in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science Series, No. 2799, edited by J. J. Chico and E. Macii, Springer, September 2003 (Int. Workshop Power and Timing Modeling, Optimization and Simulation - PATMOS, Turin, Italy, September 2003).

Σ17. C. Drosos, L. Bisdounis, D. Metafas, S. Blionas, A. Tatsaki, A multi-level hardware-software validation methodology for wireless network applications, pp. 332-341, in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science Series, No. 3254, edited by E. Macii, V. Paliouras, O. Koufopavlou, Springer, September 2004 (Int. Workshop Power and Timing Modeling, Optimization and Simulation - PATMOS, Santorini, Greece, September 2004).

Σ18. L. Bisdounis, S. Blionas, E. Macii, S. Nikolaidis, R. Zafalon, Energy-aware system-on-chip for 5 GHz wireless LAN, pp. 166-176, in Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science Series, No. 3728, edited by V. Paliouras, J. Vounckx, D. Verkest, Springer, September 2005 (Int. Workshop Power and Timing Modeling, Optimization and Simulation - PATMOS, Lueven, Belgium, September 2005).